This invention generally relates to diffusion barrier layers and more particularly to a method for depositing an adhesion/barrier layer to improve contact resistances in semiconductor features.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low RC (resistance capacitance) metal interconnect properties, particularly wherein submicron via/contact holes (inter-layer interconnects) and intra-layer interconnects with increasingly high aspect ratios.
In the fabrication of semiconductor devices, increased device density requires multiple layers, making necessary the provision a multi-layered interconnect structure. Such a multi-layered interconnect structure typically includes intra-layer conductive interconnects (wiring) and inter-layer conductive interconnects formed by openings or holes in an insulating layer (inter-metal dielectric layer). Such holes are commonly referred to as contact holes, i.e., when the hole extends through an insulating layer to an active device area, or vias, i.e., when the hole extends through an insulating layer between two conductive layers. The interface of the metal-metal contact is important since a poor contact will result in higher resistance thereby increasing current heating effects and slowing signal transport times.
In a typical process for forming multiple layer interconnect structures, such as for example, a damascene process, an insulating inter-metal dielectric (IMD) layer is deposited on a conductive layer, an opening is then anisotropically etched through the IMD by conventional photolithographic and etching techniques, followed by filling the opening with a metal such as tungsten, aluminum or copper. Excess metal remaining on the surface of the IMD layer may then be removed by a dry etchback process, for example, in the case tungsten metal is used, or a chemical-mechanical polishing (CMP), for example, in the case copper metal is used. One such method known as a dual damascene technique includes the formation of a via opening in communication with an overlying trench line to form a contiguous dual damascene where both such openings are subsequently simultaneously filled with metal to form a conductive inter-layer electrical contact (via) in communication with an intra-layer conductive line (trench line).
Signal transport speed is of great concern in the semiconductor processing art for obvious performance reasons. The signal transport speed of semiconductor circuitry varies inversely with the resistance and capacitance (RC) of the interconnections. As integrated circuits become more complex and feature sizes decrease, the effect of an RC delay becomes greater.
One way to increase the signal speed of semiconductor circuitry is to reduce the resistance of conductive interconnects. Aluminum (Al) has been conventionally used for forming conductive interconnects because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the submicron range, step coverage problems have arisen with the use of Al, decreasing the reliability of interconnections formed between different wiring layers. Decreased step coverage results in high current density and enhanced electromigration.
Copper (Cu) and copper alloys have been favorably considered for replacing Al and W in VLSI interconnect metallizations. Cu has a lower resistivity than Al, making Cu attractive for intra-layer interconnection wiring. In addition, Cu has improved electrical properties compared to W, making Cu additionally attractive for use as a conductive plug for inter-layer interconnections.
There are, however, some disadvantages with the use of Cu or Cu alloys. For example, Cu readily diffuses through silicon dioxide, a typical inter-metal dielectric (IMD) material, and into silicon elements, adversely affecting the electrical properties thereof. For example, Cu is a deep-level dopant in silicon which acts to lower the semiconductor minority lifetime and increases junction leakage current. Another problem is that Cu exhibits poor adhesion to silicon dioxide based IMD layers. The problem is exacerbated as low-k porous materials where both diffusion of copper and poor adhesion is enhanced. One solution to this problem has been to form barrier/adhesion liners to line the anisotropically etched semiconductor feature prior to depositing the metal filling. Titanium nitride is commonly used as an adhesion/barrier layer since it is thermodynamically stable and is relatively impermeable to diffusing atoms and improves the adhesion of metal plugs, for example Cu or tungsten (W). A layer of titanium is frequently first deposited over the underlying material layer, frequently conductive areas of metal or silicon to improve (lower) the specific electrical contact resistance.
Tungsten is still preferred for use in the lower metallization layers adjacent to the silicon substrate since it provides an effective diffusion barrier to metal diffusion from overlying metallization layers to react with the silicon substrate. Tungsten further has high resistance to electromigration and can effectively be used to fill high aspect ratio vias by chemical vapor deposition (CVD) processes. In the use of Ti/TiN adhesion/barrier layers in tungsten filled damascenes the TiN nitride layer further operates to protect the Ti layer from reaction with tungsten CVD precursors such as WF6 which typically causes xe2x80x98volcanoxe2x80x99 defects.
One recurring problem with forming vias is the contact resistance of the metal filled via with the underlying landing layer, for example, silicon or metal. For example, residual contamination including organic residuals, for example fluoropolymers and native oxide formation over the underlying landing layer act to increase specific contact resistances. Various pre-cleaning approaches have been proposed to eliminate the problem of high contact resistivity including various forms of plasma pre-cleaning, often referred to as reactive pre-cleaning. One reactive pre-cleaning method that has been previously proposed for cleaning process in connection with silicided titanium layers has included fluorine containing gases.
It has been found that methods of reactive pre-cleaning in the prior art have resulted in decreased adhesion between a titanium containing layer and an underlying landing layer, for example silicon or metal. For example, frequently, during subsequent processes following filling of the via or damascene with metal including CMP processes it has been found that induced stresses have caused titanium containing layers to separate from the underlying landing layer. As a result, an electrically discontinuous pathway, often referred to as an Rc open, is formed thereby often requiring scrapping of the device, the presence of an Rc open otherwise known as a xe2x80x98killer defectxe2x80x99.
There is therefore a need in the semiconductor processing art to develop a reactive pre-cleaning process whereby adhesion/barrier may be reliably deposited including retaining an adhesion to an underlying landing layer.
It is therefore an object of the invention to present a reactive pre-cleaning process whereby adhesion/barrier may be reliably deposited including retaining an adhesion to an underlying landing layer while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming an adhesion/barrier liner to improve adhesion and a specific contact resistance of semiconductor wafer metal interconnects.
In a first embodiment the method includes providing a semiconductor wafer having a process surface including an etched opening extending through a dielectric insulating layer thickness and in closed communication with a conductive underlayer surface; pre-heating the semiconductor wafer in a plasma reactor to a pre-heating temperature of at least 400xc2x0 C.; cleaning the etched opening according to a plasma assisted reactive pre-cleaning process (RPC) comprising nitrogen trifluoride (NF3); and, blanket depositing at least a first adhesion/barrier layer over the etched opening substantially free of fluorine containing residue.
These and other embodiments, aspects and features of the invention will become better understood from a detailed description of the preferred embodiments of the invention which are described in conjunction with the accompanying drawings.